The TSP1 Neural Network Accelerator Chip: Advancing Brain-Inspired Computing

The TSP1 accelerator chip runs Legendre Memory Units (LMUs) to deliver state-of-the-art time-series inference at milliwatt power levels.

The current trajectory of artificial intelligence is bound by a severe compute and memory bottleneck: running massive Transformer models requires data center-scale energy. Pushing complex inference to the edge—enabling low-latency, privacy-preserving, and always-available AI in smart glasses, robotics, and wearables—requires fundamentally rethinking how temporal data is processed. The Time Series Processor 1 (TSP1) from Applied Brain Research addresses this by completely departing from standard hardware architectures, instead executing highly efficient, brain-inspired State Space Models natively on silicon.

Key Takeaways

  • The Legendre Memory Unit (LMU): The algorithmic heart of the TSP1, the LMU is a State Space Model based directly on the continuous-time dynamics of time cells in the rodent hippocampus. It optimally compresses sliding windows of time-series data using orthogonal Legendre polynomials.
  • O(N) Scaling complexity: Unlike Transformers, which suffer from O(N²) scaling regarding context length, LMUs scale linearly. This allows the model to retain immense contextual memory with drastically smaller parameter counts and reduced training data requirements.
  • Natively streaming by design: LMUs are continuous dynamical networks perfectly suited for “batch one” streaming data (audio, RF signals, medical vitals), bypassing the latency introduced by windowed batch processing.
  • Extreme hardware efficiency: The TSP1 eliminates standard instruction-fetch cycles during network execution. This highly localized data flow results in nearly a terabyte-per-second-per-watt of memory bandwidth, achieving cloud-level Automatic Speech Recognition (ASR) and Text-to-Speech (TTS) at around 35 milliwatts of power.

Workshop Format & Takeaways

The workshop provided a unified narrative stretching from theoretical neuroscience to physical silicon. It began by comparing the spiking activity of hippocampal time cells to the continuous dynamic state vectors of the LMU algorithm. The session mapped the LMU’s rapid ascent in NLP benchmarks, proving its parameter efficiency over LSTMs and Transformers. Finally, a live demonstration showcased the TSP1 chip processing raw audio, performing highly accurate, real-time speech transcription and natural-sounding voice generation while remaining entirely untethered from the cloud.

What This Means for Neuromorphic Computing

The TSP1 demonstrates the profound commercial and computational leverage gained through strict algorithm-hardware co-design. As highlighted during the session, much of the industry’s power is wasted shuffling massive matrices between memory and compute cores to satisfy the batch-heavy demands of Transformers.

By observing how the brain handles temporal continuity—processing streams of data continuously rather than buffering them into static snapshots—Applied Brain Research developed an algorithm that inherently requires less data movement. Baking that specific dynamic directly into the TSP1’s digital architecture proves that achieving extreme edge AI does not strictly require analog substrates or asynchronous spikes; it requires abandoning von Neumann bottlenecks in favor of localized, continuous-time dynamics.

Resources

About the Speakers

Chris Eliasmith

Chris Eliasmith

Professor, Canada Research Chair in Theoretical Neuroscience, and CTO at Applied Brain Research. Research focuses on large-scale brain modelling, neural dynamics, efficient AI, and neuromorphic engineering.
Danny Rosen

Danny Rosen

Danny Rosen is a Master’s student in Computer Engineering at Virginia Tech’s Innovation Campus in Alexandria, Virginia. He’s currently researching Spiking Neural Networks (SNNs) for edge-based signal processing.
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